According to the Moore's law, the sizes of semiconductor devices are decreasing. The number of transistors integratable on one LSI chip has doubled in two years, and the processing performance of LSI chips is together with it exponentially improving at an annual rate of 70%. In recent years, however, limitations to the Moore's law have been pointed out. The problem pointed out is an increase in chip production cost. As the micro-processing in a production process has advanced, a mask cost and a lithography apparatus cost have been increasing, and the costs for researches and developments have been increasing. As an effective method therefor, three-dimensional assembly has been focused on, and it is highlighted as one of “More than Moore” techniques that break through the limitation of the Moore's law without relying on the decreasing of device sizes. That is, when chips are vertically stacked to make three-dimensional integration, the integration degree can be improved without relying on a cutting-edge micro-processing, and an integration degree over the Moore's law can be materialized.
The key to the three-dimensional assembly exists in the technique of electrical contacting between stacked chips. In a conventional three-dimensional assembly, the stacked chips are connected by wire bonding. The wire bonding causes a reflection noise during high-frequency signaling since the wire has a large length.
In contrast, in the three-dimensional assembly using through-silicon via electrodes (TSV), the wiring length is small, and the property of high-frequency signaling is greatly improved (for example, see Patent Document 1). As a result, the wiring length can be decreased by connecting the stacked chips at a small distance in the perpendicular direction with a through-silicone via electrode. When chips are three-dimensionally assembled using through-silicon via electrodes and are used in a device, the decrease in thickness, downsizing, higher-scale integration and higher-speed of a device can be achieved simultaneously, and most recently, such three-dimensional assemblies have been rapidly developed and practically used.
The process of making a through-silicon via electrode for use therein comprises (1) forming a non-through via hole having an unconventionally high aspect ratio (depth/opening diameter) in a silicon substrate by drying etching, (2) metallizing the silicon substrate having the via hole with copper by electroplating, and (3) applying CMP to the metalized silicon substrate to make a silicon chip having a front surface and a back surface that are connected through the via hole filled with copper that is a conductive material.
The greatest problem with the above process is in the (2) step of metallization with copper. That is, a via hole having a very high aspect ratio, e.g., an aspect ratio of 5 or more, is filled with copper, an opening portion of a via hole having a bottom is liable to be closed before the via hole is internally fully filled, and as a result, a narrow long hollow portion, i.e., a void is liable to be formed in the center portion of the via hole from the opening portion to the bottom. When a chip has such a void, highly acidic plating liquid is liable to remain in the void, and impractically, the lifetime of the chip is liable to be decreased. For preventing the formation of the void, it is effective to decrease the current density in the step of metallization with copper (e.g., 1 mA/cm2, see Patent Document 2). In this case, however, there is involved a problem that the plating takes a long time (e.g., approximately 10 hours), which leads to poor productivity.
That is, with demands to develop a through-silicon via (TSV), it is required to increase the aspect ratio of vias of a silicone substrate. In this case, there are contradicting problems of the occurrence of a void and a longer time period that the plating takes. It has been hence demanded to overcome them at the same time.